For example, a significant characteristic of a CMOS (Complementary Metal Oxide Semiconductor) circuit resides in a scaling rule that when an element size is miniaturized, an increase in an operational speed and a reduction in power consumption can be realized. Heretofore, a degree of integration per chip and performance have been promoted by miniaturization of the element. However, with a progress in miniaturization, the promotion of the degree of integration and the chip performance tend to slow down. The reason is that there is a limit in the miniaturization per se, a delay in wirings among elements is actualized by an increase in the speed of the element, and the reduction in power consumption becomes difficult by a problem of leakage by miniaturizing the element.
On the other hand, when an information processing system of a constant scale is constructed, there is a limit in a function of enabling integration on one chip, and therefore, it is indispensable to arrange plural chips and connect the chips. Heretofore, a direction of arranging chips is horizontal, and a distance of transmitting signals among chips becomes a length equal to or larger than one side length of the chip. Therefore, even when the operational speed per chip is increased by miniaturization, time is still taken in transmission among chips, and therefore, an increase in a speed of a system as a whole is difficult.
In order to deal with slow down in promotion of the chip function and promotion of function of the system as a whole, there is proposed a stacked chip system represented by Takahashi, eight others: Current Status of Research and Development for Three-Dimensional Chip Stack Technology, JAPANESE JOURNAL OF APPLIED PHYSICS, Vol. 40, 2001, pp. 3032-3037. The outline is shown in FIG. 1A. This is a technology of transmitting information or power by three-dimensionally stacking other circuit chips upward and downward from a semiconductor chip 100 and connecting the chips by a through-via-hole. It can be expected that a delay by wirings among elements in the chip and a delay by transmission among chips which becomes a bottleneck in a total of the system is considerably reduced by transmitting a signal in a long distance wiring of the chip or a wiring among chips by a through-via-hole right above the chip.
The through-via-hole used here is constituted by a structure of penetrating head and tail of a chip literally by a penetrated conductor 101. The penetrated conductor 101 is brought into contact with a pad 102 in a circuit forming layer 111, and the pad 102 is brought into contact with a penetrated conductor of another chip via a solder bump 104. The chip at the lowest layer is brought into contact with a package board 112 etc. via the solder bump 104. An insulating film 103 is formed at a surrounding of the penetrated conductor 101. A semiconductor substrate layer 110 constituting the chip is substantially at the ground potential, and therefore, it is necessary to insulate a portion at which the penetrated conductor and the semiconductor substrate layer 110 are brought into contact with each other.
Further, for example, JP-A-2006-330974 discloses a technology of realizing high speed data transmission by inserting a latch circuit at a data signal path of a through-via-hole, making a total of a stacked layer system carry out a pipeline operation, and isolating a parasitic capacitance by the latch circuit.